1. Field of the Invention
This invention relates to data processing systems and more particularly to apparatus for testing memory refresh logic.
2. Description of the Prior Art
Data processing systems include metal oxide semiconductor (MOS) dynamic random access memories. Information stored in MOS memories must be refreshed periodically, particularly in those address locations in which there is little activity. Failure of the refresh logic results in intermittent errors, the cause of which is difficult to determine.
A typical system is described in U.S. Pat. No. 4,317,169 entitled "Data Processing System Having Centralized Memory Refresh" which provides logic within the CPU to signal the MOS memory that a memory refresh operation can be performed. Logic in the MOS memory may either accept or discard the memory refresh signals that would refresh memory more frequently than required.
A technique for testing and verifying the operation of MOS memories is described in U.S. Pat. No. 4,359,771 entitled "Method and Apparatus for Testing and Verifying the Operation of Error Control Apparatus Within a Memory". Soft error rewrite control apparatus, in conjunction with error correction and detection (EDAC) circuits, writes corrected versions of the information read out from each location of a memory module at a predetermined rate.
Neither of these systems provides a means for verifying the refresh logic.
There is a need for data processing systems to have the means for readily testing the refresh logic of dynamic MOS memories. Improper operation of the refresh logic results in intermittent errors, the sources of which are difficult to locate.